Field
The present disclosure generally relates to integrated circuits (ICs). More specifically, one aspect of the present disclosure relates to an electrically reconfigurable interposer with built-in resistive memory.
Background
The process flow for semiconductor fabrication of integrated circuits (ICs) may include front-end-of-line (FEOL), middle of line (MOL), and back-end-of-line (BEOL) processes. The FEOL process may include wafer preparation, isolation, well formation, gate patterning, spacer, extension and source/drain implantation, silicide formation, and dual stress liner formation. The MOL process may include gate contact formation. Middle of line layers may include, but are not limited to, MOL contacts, vias or other layers within close proximity to the semiconductor device transistors or other like active devices. The BEOL processes may include a series of wafer processing steps for interconnecting the semiconductor devices created during the FEOL and MOL processes. Successful fabrication of modern semiconductor chip products involves an interplay between the materials and the processes employed.
An interposer is a die-mounting technology in which the interposer serves as a base upon which the semiconductor dies of a system on chip (SoC) are mounted. An interposer may include wiring layers of conductive traces and conductive vias for routing electrical connections between the semiconductor dies (e.g., memory modules and processors). In most applications, the interposer does not include active devices such as diodes and transistors.